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2024 Introduction to HPC for Computational Scientists Seminar
Use of High-Performance Computing (HPC) infrastructure is becoming increasingly important to researchers, however as many conventional scaling regimes break down hardware manufacturers are developing a variety of approaches to continue advancing compute performance. These different approaches may have significant implications for code performance and often require the user to be aware of them if you wish to extract the best possible performance/efficiency. This seminar is intended primarily for HPC users who may not have a background in computer science & engineering, having entered the field from a different pathway.
This seminar covers the basics of computer hardware design and operation and how this can affect program operation. Beginning with a simple in-order scalar CPU design, we will cover the evolution of techniques used to improve performance over the last ~30 years and what this means for our mental model of CPU operation, as well as how GPUs diverge from that paradigm. We then explore how modern computing is typically limited by our ability to transfer data rather than operate on it (the memory wall) and the trade-offs of cache hierarchies and interconnect choices used to offset this limitation. Finally, we delve into how interconnects have evolved and how the current proliferation in hardware design strategies by different vendors affects code execution, giving specific reference to consumer-grade hardware and that found in the NCI Gadi and Pawsey Setonix supercomputers.